Clock Jitter and Excess Loop Delay in Continuous-Time Delta-Sigma Modulators
نویسنده
چکیده
Continuous-time ∆Σ modulators are able to operate at higher frequencies than their discrete-time counterparts. However, they suffer more severely from non-idealities such as clock jitter and excess loop delay. The effects of these two non-idealities are explained and a continuous-time to discrete-time conversion method is presented in order to aid in the analysis of these non-idealities. Two circuits are presented that alleviate these problems: the SC-R feedback circuit helps eliminate clock jitter noise while the compensation solution lessens the effects of excess loop delay.
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